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| Acadêmico(a): André Leonardo Bieging |
| Título: Implementação M++ em FPGA |
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| Abstract: |
| This project’s objective is to implement de M++ architecture in the FPGA platform. The hardware description language Verilog was used. The first step to develop the project was to list the needed functional and non-functional requisites, to then create the project’s specification, which is a detailed description of the M++ architecture. For the specification’s implementation, the Quartus IDE was used to develop and compile the code and its TimeQuest Timing Analyzer extension calculated the design timings, while the software ModelSim*-Intel® FPGA edition was used to simulate the design. The program MontadorMmaismais was necessary to develop the test programs and the program MapReader was developed to convert .map files into Verilog programs. The final result was a design capable of executing the instructions defined by the specification and has a maximum working frequency that’s much higher than what is possible with the M++’s current simulation software. Based on the achieved results, it’s concluded that it’s possible to implement the M++’s architecture in Verilog and achieve a design with a considerable performance. |
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